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https://cern.zoom.us/j/4042031778
ML@FPGA:

Optimization of Conv2D: parallelization of convolution pipelining
unroll width loop by a factor of kernel size (3) can avoid memory r/w conflict
latency: 10.56us (95kHz) -> 1.58us (0.6MHz)
Ideal: ~250ns (4MHz) (unroll height loop)
Timing Violation:
DarkSHINE: