[2025-01-18] For better promotion of the events, the categories in this system will be adjusted. For details, please refer to the announcement of this system. The link is https://indico-tdli.sjtu.edu.cn/news/1-warm-reminder-on-adjusting-indico-tdli-categories-indico
点击链接入会,或添加至会议列表:
https://cern.zoom.us/j/4042031778?pwd=N0RlZ0l3dGtEYk9zT25OWmlwVklSZz09
ML@FPGA:

Optimization of Conv2D: parallelization of convolution pipelining
unroll width loop by a factor of kernel size (3) can avoid memory r/w conflict
latency: 10.56us (95kHz) -> 1.58us (0.6MHz)
Ideal: ~250ns (4MHz) (unroll height loop)
Timing Violation:
DarkSHINE: